XDR DRAM is also known as extreme data rate or a dynamic random access memory. It is a high performance RAM interface and is seen as an effective successor to Rambus RDRAM. The specialty of DRAM is that it stores each bit of data in a separate capacitor with an integrated circuit.

XDR was designed to be effective in small, high performance memory application and high end GPUs. XDR is basically used by Sony in play station 3 consoles.

Performance – at present the initial clock rate is at 400 MHz, and 600 MHz, 800 MHz and 1066 MHz models are being planned for the future. Octal data rate is around Eight bits per clock cycle per lane. Each chip provides up to 230.4 Gbit/s and the chip provides 8, 16 or 32 programmable lanes.

Features – There is a Bi-directional differential Rambus Signalling Levels (DRSL) which uses open collector driver and voltage swing 0.2V. There is a programmable on chip termination feature. There is 8 bank memory architecture, Adaptive impedance matching, dynamic request scheduling, and zero overhead refresh, Early-read-after-write support for maximum efficiency, Point-to-point data interconnection feature and Chip scale package packaging.

Power requirements – The system consists of low power PLL/DLL design, 1.8 V VDD, Programmable ultra-low-voltage DRSL 200 mV swing, Power-down self-refresh support, Dynamic data width support with dynamic clock gating, Per-pin I/O power-down and Sub-page activation support.

The system design consists of Per-bit FlexPhase circuits compensate to a 2.5 ps resolution and an XDR Interconnect using minimum pin count.

Protocol – XDR DRAM consists of high speed signals which are differential clock input, a 12 bit single- ended request/command bus. This request bus may be connected to several memory chips in parallel connection, but the data bus is point to point. But it should be ensured that only one ram chip may be connected to it.

Hence XDR DRAM is an effective one which eliminates high latency problems, these lay high emphasis on per pin bandwidth which can further benefit cost control.